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A6275elw data sheet 26185.200b? 8-bit serial-input, constant- current latched led driver always order by complete part number, e.g., A6275ea . the A6275ea and A6275elw are specifically designed for led- display applications. each bicmos device includes an 8-bit cmos shift register, accompanying data latches, and eight npn constant- current sink drivers. except for package style and allowable package power dissipation, the two devices are identical. the cmos shift register and latches allow direct interfacing with microprocessor-based systems. with a 5 v logic supply, typical serial data-input rates are up to 20 mhz. the led drive current is deter- mined by the user? selection of a single resistor. a cmos serial data output permits cascade connections in applications requiring additional drive lines. for inter-digit blanking, all output drivers can be disabled with an enable input high. similar 150 ma output devices are available as the a6277ea and a6277elw; similar 16-bit devices are available as the a6276ea and a6276elw. two package styles are provided for through-hole dip (suffix a) or surface-mount soic (suffix lw). under normal applications, copper lead frames and low logic-power dissipation allow these devices to sink maximum rated current through all outputs continuously over the operating temperature range (90 ma, 0.9 v drop, +85 c). both devices are also available for operation over the standard temperature range of -20 c to +85 c. to order, change the suffix letter ??to ?? absolute maximum ratings supply voltage, v dd ...................... 7.0 v output voltage range, v o ............................ -0.5 v to +17 v output current, i o ........................ 90 ma ground current, i gnd ................. 750 ma input voltage range, v i .................... -0.4 v to v dd + 0.4 v package power dissipation, p d ..................................... see graph operating temperature range, t a ............................. -40 c to +85 c storage temperature range, t s ........................... -55 c to +150 c caution: these cmos devices have input static protection (class 2) but are still suscep- tible to damage if exposed to extremely high static electrical charges. ground register latches 1 2 3 89 10 11 12 13 15 4 5 6 7 14 16 serial data out logic supply serial data in output enable latch enable clock ck v dd oe out 1 out 2 dwg. pp-029-10 out 0 out 4 out 6 out 5 out 3 out 7 r ext i regulator l o note that the A6275ea (dip) and the A6275elw (soic) are electrically identical and share a common terminal number assignment. 6275 features to 90 ma constant-current outputs under-voltage lockout low-power cmos logic and latches high data input rate pin-compatible with tb62705cp
115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 6275 8-bit serial-input, constant-current latched led driver 2 copyright ?2000, 2003 allegro microsystems, inc. 50 75 100 125 150 2.5 0.5 0 ambient temperature in c 2.0 1.5 1.0 25 dwg. gp-018c suffix 'a', r = 60 c/w ja suffix 'lw', r = 94 c/w ja allowable package power dissipation in watts functional block diagram mos bipolar ground latch enable output enable (active low) serial data out clock serial data in serial-parallel shift register latches v dd logic supply r ext out 0 out 1 dwg. fp-013-3 out 2 out n i regulator o uvlo
6275 8-bit serial-input, constant-current latched led driver www.allegromicro.com 3 clock and serial data in serial data out latch enable output enable (active low) dwg. ep-010-11 in v dd dwg. ep-010-12 in v dd dw g . ep-010-13 in v dd truth table serial shift register contents serial latch latch contents output output contents data clock data enable enable input input i 1 i 2 i 3 ... i n-1 i n output input i 1 i 2 i 3 ... i n-1 i n input i 1 i 2 i 3 ... i n-1 i n hhr 1 r 2 ... r n-2 r n-1 r n-1 llr 1 r 2 ... r n-2 r n-1 r n-1 xr 1 r 2 r 3 ... r n-1 r n r n xxx...x x x l r 1 r 2 r 3 ... r n-1 r n p 1 p 2 p 3 ... p n-1 p n p n hp 1 p 2 p 3 ... p n-1 p n lp 1 p 2 p 3 ... p n-1 p n xxx...x x h h h h ... h h l = low logic (voltage) level h = high logic (voltage) level x = irrelevant p = present state r = previous state v dd dw g . ep-063-6 out
115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 6275 8-bit serial-input, constant-current latched led driver 4 electrical characteristics at t a = +25 c, v dd = 5 v (unless otherwise noted). limits characteristic symbol test conditions min. typ. max. unit supply voltage range v dd operating 4.5 5.0 5.5 v under-voltage lockout v dd(uv) v dd = 0 5 v 3.4 C 4.0 v output current i o v ce = 0.7 v, r ext = 250 ? 64.2 75.5 86.8 ma (any single output) v ce = 0.7 v, r ext = 470 ? 34.1 40.0 45.9 ma output current matching ? i o 0.4 v v ce(a) = v ce(b) 0.7 v: (difference between any r ext = 250 ? C 1.5 6.0 % two outputs at same v ce ) r ext = 470 ? C 1.5 6.0 % output leakage current i cex v oh = 15 v C 1.0 5.0 a logic input voltage v ih 0.7v dd Cv dd v v il gnd C 0.3v dd v serial data out v ol i ol = 500 a C C 0.4 v voltage v oh i oh = -500 a 4.6 C C v input resistance r i enable input, pull up 150 300 600 k ? latch input, pull down 100 200 400 k ? supply current i dd(off) r ext = open, v oe = 5 v C 0.8 1.4 ma r ext = 470 ? , v oe = 5 v 3.5 6.0 8.0 ma r ext = 250 ? , v oe = 5 v 6.5 11 15 ma i dd(on) r ext = 470 ? , v oe = 0 v 5.0 10 14 ma r ext = 250 ? , v oe = 0 v 8.0 16 24 ma typical data is at v dd = 5 v and is for design information only.
6275 8-bit serial-input, constant-current latched led driver www.allegromicro.com 5 recommended operating conditions characteristic symbol conditions min. typ. max. unit supply voltage v dd 4.5 5.0 5.5 v output voltage v o C 1.0 4.0 v output current i o continuous, any one output C C 90 ma i oh serial data out C C -1.0 ma i ol serial data out C C 1.0 ma logic input voltage v ih 0.7v dd Cv dd + 0.3 v v il -0.3 C 0.3v dd v clock frequency f ck cascade operation C C 10 mhz switching characteristics at t a = 25 c, v dd = v ih = 5 v, v ce = 0.4 v, v il = 0 v, r ext = 470 ? , i o = 40 ma, v l = 3 v, r l = 65 ? , c l = 10.5 pf. limits characteristic symbol test conditions min. typ. max. unit propagation delay time t phl clock-out n C 350 1000 ns latch-out n C 350 1000 ns enable-out n C 350 1000 ns clock-serial data out C 40 C ns propagation delay time t plh clock-out n C 300 1000 ns latch-out n C 300 1000 ns enable-out n C 300 1000 ns clock-serial data out C 40 C ns output fall time t f 90% to 10% voltage 150 350 1000 ns output rise time t r 10% to 90% voltage 150 300 600 ns
115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 6275 8-bit serial-input, constant-current latched led driver 6 timing requirements and specifications (logic levels are v dd and ground) a. data active time before clock pulse (data set-up time), t su(d) .......................................... 60 ns b. data active time after clock pulse (data hold time), t h(d) .............................................. 20 ns c. clock pulse width, t w(ck) ............................................... 50 ns d. time between clock activation and latch enable, t su(l) ............................................ 100 ns e. latch enable pulse width, t w(l) ................................... 100 ns f. output enable pulse width, t w(oe) ................................ 4.5 s note ?timing is representative of a 10 mhz clock. significantly higher speeds are attainable. max. clock transition time, t r or t f .............................. 10 s information present at any register is transferred to the respective latch when the latch enable is high (serial-to- parallel conversion). the latches will continue to accept new data as long as the latch enable is held high. applica- tions where the latches are bypassed (latch enable tied high) will require that the output enable input be high during serial data entry. when the output enable input is high, the output source drivers are disabled (off). the information stored in the latches is not affected by the output enable input. with the output enable input low, the outputs are controlled by the state of their respective latches. clock serial data in latch enable output enable out n dwg. wp-029-1 50% serial data out data data 50% 50% 50% c a b d e low = all outputs enabled p t data 50% p t low = output on high = output off output enable out n dwg. wp-030-1a data 10% 50% phl t plh t high = all outputs disabled (blanked) f t r t 90% f 50%
6275 8-bit serial-input, constant-current latched led driver www.allegromicro.com 7 allowable output current as a function of duty cycle A6275ea A6275elw 0 20 duty cycle in per cent 100 0 dwg. gp-062-5 allowable output current in ma/bit 60 40 20 40 60 100 80 v ce = 2 v v ce = 3 v v ce = 4 v 80 t a = +25 c v dd = 5 v r ja = 60 c/w 0 20 duty cycle in per cent 100 0 dwg. gp-062-3 allowable output current in ma/bit 60 40 20 40 60 100 80 v ce = 2 v v ce = 3 v v ce = 4 v 80 t a = +50 c v dd = 5 v r ja = 60 c/w 020 duty cycle in per cent 100 0 dwg. gp-062-2a allowable output current in ma/bit 60 40 20 40 60 100 80 v ce = 1 v v ce = 2 v v ce = 3 v v ce = 4 v 80 t a = +50 c v dd = 5 v r ja = 94 c/w 020 duty cycle in per cent 100 0 dwg. gp-062-4a allowable output current in ma/bit 60 40 20 40 60 100 80 v ce = 2 v v ce = 3 v v ce = 1 v v ce = 4 v 80 t a = +25 c v dd = 5 v r ja = 94 c/w
115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 6275 8-bit serial-input, constant-current latched led driver 8 0 20 duty cycle in per cent 100 0 dwg. gp-062-1 allowable output current in ma/bit 60 40 20 40 60 100 80 v ce = 1 v v ce = 2 v v ce = 3 v v ce = 4 v 80 t a = +85 c v dd = 5 v r ja = 60 c/w 020 duty cycle in per cent 100 0 dwg. gp-062a allowable output current in ma/bit 60 40 20 40 60 100 80 v ce = 1 v v ce = 2 v v ce = 3 v 80 t a = +85 c v dd = 5 v r ja = 94 c/w v ce = 0.7 v v ce = 4 v allowable output current as a function of duty cycle (cont.) A6275ea A6275elw typical characteristics 0.5 dwg. gp-063 1.0 2.0 1.5 v ce in volts 0 60 40 output current in ma/bit 20 0 t a = +25 c r ext = 500 ?
6275 8-bit serial-input, constant-current latched led driver www.allegromicro.com 9 terminal description terminal no. terminal name function 1 gnd reference terminal for control logic. 2 serial data in serial-data input to the shift-register. 3 clock clock input terminal for data shift on rising edge. 4 latch enable data strobe input terminal; serial data is latched with high-level input. 5-12 out 0-7 the eight current-sinking output terminals. 13 output enable when (active) low, the output drivers are enabled; when high, all output drivers are turned off (blanked). 14 serial data out cmos serial-data output to the following shift-register. 15 r ext an external resistor at this terminal establishes the output current for all sink drivers. 16 supply (v dd ) the logic supply voltage (typically 5 v). the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. the information included herein is believed to be accurate and reliable. however, allegro microsystems, inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 6275 8-bit serial-input, constant-current latched led driver 10 the load current per bit (i o ) is set by the external resistor (r ext ) as shown in the figure below. 300 500 700 1 k 2 k current-control resistance, r ext in ohms 100 0 100 dwg. gp-061 output current in ma/bit 5 k 200 3 k 20 40 60 80 v ce = 0.7 v package power dissipation (p d ). the maximum allowable package power dissipation is determined as p d (max) = (150 - t a )/r ja . the actual package power dissipation is p d (act) = dc(v ce ?i o ?8) + (v dd ?i dd ). when the load supply voltage is greater than 3 v to 5 v, considering the package power dissipating limits of these devices, or if p d (act) > p d (max), an external voltage reducer (v drop ) should be used. load supply voltage (v led ). these devices are designed to operate with driver voltage drops (v ce ) of 0.4 v to 0.7 v with led forward voltages (v f ) of 1.2 v to 4.0 v. if higher voltages are dropped across the driver, package power dissipation will be increased significantly. to minimize package power dissipation, it is recom- mended to use the lowest possible load supply voltage or to set any series dropping voltage (v drop ) as v drop = v led - v f - v ce with v drop = i o ?r drop for a single driver, or a zener diode (v z ), or a series string of diodes (approximately 0.7 v per diode) for a group of drivers. if the available voltage source will cause unacceptable dissipation and series resistors or diode(s) are undesirable, a regulator such as the sanken series sai or series si can be used to provide supply voltages as low as 3.3 v. for reference, typical led forward voltages are: white 3.5 ?4.0 v blue 3.0 ?4.0 v green 1.8 ?2.2 v yellow 2.0 ?2.1 v amber 1.9 ?2.65 v red 1.6 ?2.25 v infrared 1.2 ?1.5 v pattern layout. this device has a common logic- ground and power-ground terminal. if ground pattern layout contains large common-mode resistance, and the voltage between the system ground and the latch enable or clock terminals exceeds 2.5 v (because of switching noise), these devices may not operate correctly. dw g . ep-064 v led v drop v f v ce applications information
6275 8-bit serial-input, constant-current latched led driver www.allegromicro.com 11 A6275ea dimensions in inches (controlling dimensions) dimensions in millimeters (for reference only) notes: 1. exact body and lead configuration at vendor? option within limits shown. 2. lead spacing tolerance is non-cumulative 3. lead thickness is measured at seating plane or below. 4. supplied in standard sticks/tubes of 25 devices. 0.355 0.204 7.62 bsc dwg. ma-001-16a mm 10.92 max 16 1 8 7.11 6.10 5.33 max 1.77 1.15 0.39 min 0.558 0.356 2.54 bsc 0.13 min 3.81 2.93 9 19.68 18.67 0.014 0.008 0.300 bsc dwg. ma-001-16a in 0.430 max 16 1 8 0.280 0.240 0.210 max 0.070 0.045 0.015 min 0.022 0.014 0.100 bsc 0.005 min 0.150 0.115 9 0.775 0.735
115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 6275 8-bit serial-input, constant-current latched led driver 12 A6275elw dimensions in inches (for reference only) dimensions in millimeters (controlling dimensions) notes: 1. exact body and lead configuration at vendor s option within limits shown. 2. lead spacing tolerance is non-cumulative. 3. supplied in standard sticks/tubes of 47 devices or add tr to part number for tape and reel. 1 2 3 0.2992 0.2914 0.4133 0.3977 0.419 0.394 0.020 0.013 0.0926 0.1043 0.0040 min. 0.0125 0.0091 0.050 0.016 0 to 8 dwg. ma-008-16a in 0.050 bsc 16 9 9 16 1 2 3 7.60 7.40 10.50 10.10 10.65 10.00 0.51 0.33 2.65 2.35 0.10 min. 0.32 0.23 1.27 0.40 0 to 8 dwg. ma-008-16a mm 1.27 bsc

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